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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. december 1995 copyright ? intel corporation, 1996 order number: 290414-003 upi-c42/upi-l42 universal peripheral interface chmos 8-bit slave microcontroller y pin, software and architecturally compatible with all upi-41 and upi-42 products y low voltage operation with the upi- l42 e full 3.3v support y hardware a20 gate support y suspend power down mode y security bit code protection support y 8-bit cpu plus rom/otp eprom, ram, i/o, timer/counter and clock in a single package y 4096 x 8 rom/otp, 25 6 x 8 ram 8-bit timer/counter, 18 programmable i/o pins y dma, interrupt, or polled operation supported y one 8-bit status and two data registers for asynchronous slave-to- master interface y fully compatible with all intel and most other microprocessor families y interchangeable rom and otp eprom versions y expandable i/o y sync mode available y over 90 instructions: 70% single byte y quick pulse programming algorithm e fast otp programming y available in 40-lead plastic, 44-lead plastic leaded chip carrier, and 44-lead quad flat pack packages (see packaging spec., order y 240800, package type p, n, and s) the upi-c42 is an enhanced chmos version of the industry standard intel upi-42 family. it is fabricated on intel's chmos iii-e process. the upi-c42 is pin, software, and architecturally compatible with the nmos upi family. the upi-c42 has all of the same features of the nmos family plus a larger user programmable memory array (4k), hardware a20 gate support, and lower power consumption inherent to a chmos product. the upi-l42 offers the same functionality and socket compatibility as the upi-c42 as well as providing low voltage 3.3v operation. the upi-c42 is essentially a ``slave'' microcontroller, or a microcontroller with a slave interface included on the chip. interface registers are included to enable the upi device to function as a slave peripheral controller in the mcs modules and iapx family, as well as other 8-, 16-, and 32-bit systems. to allow full user flexibility, the program memory is available in rom and one-time programmable eprom (otp). 290414 1 figure 1. dip pin configuration 290414 2 figure 2. plcc pin configuration 290414 3 figure 3. qfp pin configuration
upi-c42/upi-l42 table 1. pin description dip plcc qfp symbol pin pin pin type name and function no. no. no. test 0, 1 2 18 i test inputs: input pins which can be directly tested using conditional branch instructions. test 1 39 43 16 frequency reference: test 1 (t 1 ) functions as the event timer input (under software control). test 0 (t 0 ) is a multi-function pin used during prom programming and rom/eprom verification, during sync mode to reset the instruction state to s1 and synchronize the internal clock to ph1. xtal 1 2 3 19 o output: output from the oscillator amplifier. xtal 2 3 4 20 i input: input to the oscillator amplifier and internal clock generator circuits. reset 4 5 22 i reset: input used to reset status flip-flops, set the program counter to zero, and force the upi-c42 from the suspend power down mode. reset is also used during eprom programming and verification. ss 5 6 23 i single step: single step input used in conjunction with the sync output to step the program through each instruction (eprom). this should be tied to a 5v when not used. this pin is also used to put the device in sync mode by applying 12.5v to it. cs 6 7 24 i chip select: chip select input used to select one upi microcomputer out of several connected to a common data bus. ea 7 8 25 i external access: external access input which allows emulation, testing and rom/eprom verification. this pin should be tied low if unused. rd 8 9 26 i read: i/o read input which enables the master cpu to read data and status words from the output data bus buffer or status register. a 0 91027i command/data select: address input used by the master processor to indicate whether byte transfer is data (a 0 e 0, f1 is reset) or command (a 0 e 1, f1 is set). a 0 e 0 during program and verify operations. wr 10 11 28 i write: i/o write input which enables the master cpu to write data and command words to the upi input data bus buffer. sync 11 13 29 o output clock: output signal which occurs once per upi instruction cycle. sync can be used as a strobe for external circuitry; it is also used to synchronize single step operation. d 0 d 7 (bus) 1219 1421 3037 i/o data bus: three-state, bidirectional data bus buffer lines used to interface the upi microcomputer to an 8-bit master system data bus. p 10 p 17 2734 3033 210 i/o port 1: 8-bit, port 1 quasi-bidirectional i/o lines. p 10 p 17 access the signature row and security bit. 3538 2
upi-c42/upi-l42 table 1. pin description (continued) dip plcc qfp symbol pin pin pin type name and function no. no. no. p 20 p 27 2124 2427 3942 i/o port 2: 8-bit, port 2 quasi-bidirectional i/o lines. the lower 4 bits (p 20 p 23 ) interface directly to the 8243 i/o expander device and 3538 3942 11, 1315 contain address and data information during port 4 7 access. p 21 can be programmed to provide hardware a20 gate support. the upper 4 bits (p 24 p 27 ) can be programmed to provide interrupt request and dma handshake capability. software control can configure p 24 as output buffer full (obf) interrupt, p 25 as input buffer full (ibf ) interrupt, p 26 as dma request (drq), and p 27 as dma acknowledge (dack ). prog 25 28 43 i/o program: multifunction pin used as the program pulse input during prom programming. during i/o expander access the prog pin acts as an address/data strobe to the 8243. this pin should be tied high if unused. v cc 40 44 17 power: a 5v main power supply pin. v dd 26 29 1 power: a 5v during normal operation. a 12.75v during programming operation. low power standby supply pin. v ss 20 22 38 ground: circuit ground potential. 290414 4 figure 4. block diagram 3
upi-c42/upi-l42 upi-c42/l42 product selection guide upi-c42: low power chmos version of the upi-42. device package rom otp comments 80c42 n, p s 4k rom device 82c42pc n, p, s phoenix multikey/42 firmware, ps/2 style mouse support 82c42pd n, p, s phoenix multikey/42l firmware, kbc and scc for portable apps. 82c42pe n, p, s phoenix multikey/42g firmware, energy efficient kbc solution 87c42 n, p, s 4k one time programmable version upi-l42: the low voltage 3.3v version of the upi-c42. device package rom otp comments 80l42 n, p s 4k rom device 82l42pc n, p, s phoenix multikey/42 firmware, ps/2 style mouse support 82l42pd n, p, s phoenix multikey/42l firmware, kbc and scc for portable apps. 87l42 n, p, s 4k one time programmable version n e 44 lead plcc, p e 40 lead pdip, s e 44 lead qfp, d e 40 lead cerdip kbc e key board control, scc e scan code control the intel 82c42 as shown in the upi-c42 product matrix, the upi- c42 is offered as a pre-programmed 80c42 with var- ious versions of multikey/42 keyboard controller firmware developed by phoenix technologies ltd. the 82c42pc provides a low powered solution for industry standard keyboard and ps/2 style mouse control. the 82c42pd provides a cost effective means for keyboard and scan code control for note- book platforms. the 82c42pe allows a quick time to market, low cost solution for energy efficient desk- top designs. 4
upi-c42/upi-l42 upi-42 compatible features 1. two data bus buffers, one for input and one for output. this allows a much cleaner master/slave protocol. 290414 5 2. 8 bits of status st 7 st 6 st 5 st 4 f 1 f 0 ibf obf d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 st 4 st 7 are user definable status bits. these bits are defined by the ``mov sts, a'' single byte, single cycle instruction. bits 4 7 of the acccumulator are moved to bits 4 7 of the status register. bits 0 3 of the status register are not affected. mov sts, a op code: 90h 1 001000 0 d 7 d 0 3. rd and wr are edge triggered. ibf, obf, f 1 and int change internally after the trailing edge of rd or wr . during the time that the host cpu is reading the status register, the upi is prevented from updat- ing this register or is `locked out.' 290414 6 4. p 24 and p 25 are port pins or buffer flag pins which can be used to interrupt a master proces- sor. these pins default to port pins on reset. if the ``en flags'' instruction has been execut- ed, p 24 becomes the obf (output buffer full) pin. a ``1'' written to p 24 enables the obf pin (the pin outputs the obf status bit). a ``0'' written to p 24 disables the obf pin (the pin remains low). this pin can be used to indicate that valid data is available from the upi (in output data bus buff- er). if ``en flags'' has been executed, p 25 be- comes the ibf (input buffer full) pin. a ``1'' writ- ten to p 25 enables the ibf pin (the pin outputs the inverse of the ibf status bit. a ``0'' written to p 25 disables the ibf pin (the pin remains low). this pin can be used to indicate that the upi is ready for data. data bus buffer interrupt capability 290414 7 en flags op code: 0f5h 1 111010 1 d 7 d 0 5. p 26 and p 27 are port pins or dma handshake pins for use with a dma controller. these pins default to port pins on reset. if the ``en dma'' instruction has been executed, p 26 becomes the drq (dma request) pin. a ``1'' written to p 26 causes a dma request (drq is activated). drq is deactivated by dack # rd, dack # wr, or execution of the ``en dma'' in- struction. dma handshake capability 290414 8 5
upi-c42/upi-l42 if ``en dma'' has been executed, p 27 becomes the dack (dma acknowledge) pin. this pin acts as a chip select input for the data bus buffer registers during dma transfers. en dma op code: 0e5h 1 110010 1 d 7 d 0 6. when ea is enabled on the upi, the program counter is placed on port 1 and the lower four bits of port 2 (msb e p 23 , lsb e p 10 ). on the upi this information is multiplexed with port data (see port timing diagrams at end of this data sheet). 7. the upi-c42 supports the quick pulse program- ming algorithm, but can also be programmed with the intelligent programming algorithm. (see the programming section.) upi-c42 features programmable memory size increase the user programmable memory on the upi-c42 will be increased from the 2k available in the nmos product by 2x to 4k. the larger user programmable memory array will allow the user to develop more complex peripheral control micro-code. p2.3 (port 2 bit 3) has been designated as the extra address pin required to support the programming of the extra 2k of user programmable memory. the new instruction sel pmb1 (73h) allows for ac- cess to the upper 2k bank (locations 2048 4095). the additional memory is completely transparent to users not wishing to take advantage of the extra memory space. no new commands are required to access the lower 2k bytes. the sel pmb0 (63h) has also been added to the upi-c42 instruction set to allow for switching between memory banks. extended memory program addressing (beyond 2k) for programs of 2k words or less, the upi-c42 ad- dresses program memory in the conventional man- ner. addresses beyond 2047 can be reached by ex- ecuting a program memory bank switch instruction (sel pmb0, sel pmb1) followed by a branch in- struction (jmp or call). the bank switch feature extends the range of branch instructions beyond their normal 2k range and at the same time prevents the user from inadvertently crossing the 2k boundary. program memory bank switch the switching of 2k program memory banks is ac- complished by directly setting or resetting the most significant bit of the program counter (bit 11); see figure 5. bit 11 is not altered by normal increment- ing of the program counter, but is loaded with the contents of a special flip-flop each time a jmp or call instruction is executed. this special flip-flop is set by executing an sel pmb1 instruction and reset by sel pmb0. therefore, the sel pmb instruction may be executed at any time prior to the actual bank switch which occurs during the next branch instruc- tion encountered. since all twelve bits of the pro- gram counter, including bit 11, are stored in the stack, when a call is executed, the user may jump to subroutines across the 2k boundary and the proper pc will be restored upon return. however, the bank switch flip-flop will not be altered on return. 290414 30 figure 5. program counter interrupt routines interrupts always vector the program counter to lo- cation 3 or 7 in the first 2k bank, and bit 11 of the program counter is held at ``0'' during the interrupt service routine. the end of the service routine is sig- naled by the execution of an retr instruction. inter- rupt service routines should therefore be contained entirely in the lower 2k words of program memory. the execution of a sel pmb0 or sel pmb1 instruc- tion within an interrupt routine is not recommended since it will not alter pc11 while in the routine, but will change the internal flip-flop. hardware a20 gate support this feature has been provided to enhance the per- formance of the upi-c42 when being used in a key- board controller application. the upi-c42 design has included on chip logic to support a hardware gatea20 feature which eliminates the need to pro- vide firmware to process a20 command sequences, 6
upi-c42/upi-l42 thereby providing additional user programmable memory space. this feature is enabled by the a20en instruction and remains enabled until the de- vice is reset. it is important to note that the execu- tion of the a20en instruction redefines port 2, bit 1 as a pure output pin with read only characteristics. the state of this pin can be modified only through a valid ``d1'' command sequence (see table 1). once enabled, the a20 logic will process a ``d1'' com- mand sequence (write to output port) by setting/re- setting the a20 bit on port 2, bit 1 (p2.1) without requiring service from the internal cpu. the host can directly control the status of the a20 bit. at no time during this host interface transaction will the ibf flag in the status register be activated. table 1 gives several possible gatea20 command/data se- quences and upi-c42 responses. table 1. d1 command sequences a0 r/w db pins ibf a20 comments 1 w d1h 0 n (1) set a20 sequence 0 w dfh 0 1 only db1 is processed 1 w ffh (2) 0n 1 w d1h 0 n clear a20 sequence 0 w ddh 0 0 1 w ffh 0 n 1 w d1h 0 n double trigger set 1 w d1h 0 n sequence 0 w dfh 0 1 1 w ffh 0 n 1 w d1h 0 n invalid sequence 1 w xxh (3) 1 n no change in state 0 w ddh 1 n of a20 bit notes: 1. indicates that p2.1 remains at the previous logic level. 2. only ffh commands in a valid a20 sequence have no effect on ibf. an ffh issued at any other time will activate ibf. 3. any command except d1. the above sequences assume that the gatea20 logic has been enabled via the a20en instruction. as noted, only the value on db 1 (data bus, bit 1) is processed. this bit will be directly passed through to p2.1 (port 2, bit 1). suspend the execution of the suspend instruction (82h or e2h) causes the upi-c42 to enter the suspend mode. in this mode of operation the oscillator is not running and the internal cpu operation is stopped. the upi-c42 consumes s 40 m a in the suspend mode. this mode can only be exited by reset. cpu operation will begin from pc e 000h when the upi-c42 exits from the suspend power down mode. suspend mode summary # oscillator not running # cpu operation stopped # ports tristated with weak ( e 210 m a) pull-up # micropower mode (i cc s 40 m a) # this mode is exited by reset 7
upi-c42/upi-l42 table 2 covers all suspend mode pin states. in addi- tion to the suspend power down mode, the upi-c42 will also support the nmos power down mode as outlined in chapter 4 of the upi-42ah users manual. table 2. suspend mode pin states pins suspend ports 1 and 2 outputs tristate inputs weak pull-up disabled dbb (1) outputs normal inputs normal system control disabled (rd y ,wr y , cs y , a0) reset y enabled crystal osc. disabled (xtal1, xtal2) test 0, test 1 disabled prog high sync high ea disabled, no pull-up ss y disabled, weak pull-up i cc k 40 m a notes: 1. dbb outputs are tristate unless cs y and rd y are ac- tive. dbb inputs are disabled unless cs y and wr y are active. 2. a ``disabled'' input will not cause current to be drawn regardless of input level (within the supply range). 3. weak pull-ups have current capability of typically 5 m a. new upi-c42 instructions the upi-c42 will support several new instructions to allow for the use of new c42 features. these in- structions are not necessary to the user who does not wish to take advantage of any new c42 function- ality. the c42 will be completely compatible with all current nmos code/applications. in order to use new features, however, some code modifications will be necessary. all new instructions can easily be in- serted into existing code by use of the asm-48 mac- ro facility as shown in the following example: macname macro db 63h endm new instructions the following is a list of additions to the upi-42 in- struction set. these instructions apply only to the upi-c42. these instructions must be added to exist- ing code in order to use any new functionality. sel pmb0 select program memory bank 0 opcode 0110 0011 (63h) pc bit 11 is set to zero on next jmp or call instruc- tion. all references to program memory fall within the range of 0 2047 (0 7ffh). sel pmb1 select program memory bank 1 opcode 0111 0011 (73h) pc bit 11 is set to one on next jmp or call instruc- tion. all references to program memory fall within the range of 2048 4095 (800h fffh). ena20 enables auto a20 hardware opcode 0011 0011 (33h) enables on chip logic to support hardware a20 gate feature. will remain enabled until device is reset. 8
upi-c42/upi-l42 this circuitry gives the host direct control of port 2 bit 1 (p2.1) without intervention by the internal cpu. when this opcode is executed, p2.1 becomes a ded- icated output pin. the status of this pin is read-able but can only be altered through a valid ``d1'' com- mand sequence (see table 1). suspend invoke suspend power down mode opcode 1000 0010 (82h) or 1110 0010 (e2h) enables device to enter micro power mode. in this mode the external oscillator is off, cpu operation is stopped, and the port pins are tristated. this mode can only be exited via a reset signal. programming and verifying the upi-c42 the upi-c42 programming will differ from the nmos device in three ways. first, the c42 will have a 4k user programmable array. the upi-c42 will also be programmed using the intel quick-pulse program- ming algorithm. finally, port 2 bit three (p2.3) will be used during program as the extra address pin re- quired to program the upper 2k bank of additional memory. none of these differences have any effect on the full chmos to nmos device compatibility. the extra memory is fully transparent to the user who does not need, or want, to use the extra memo- ry space of the upi-c42. in brief, the programming process consists of: acti- vating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. each word is programmed com- pletely before moving on to the next and is followed by a verification step. the following is a list of the pins used for programming and a description of their functions: pin function xtal 2 clock input reset initialization and address latching test 0 selection of program or verify mode ea activation of program/verify signature row/security bit modes bus address and data input data output during verify p 2023 address input v dd programming power supply prog program pulse input warning an attempt to program a missocketed upi-c42 will result in severe damage to the part. an indication of a properly socketed part is the appearance of the sync clock output. the lack of this clock may be used to disable the program- mer. the program/verify sequence is: 1. insert 87c42 in programming socket 2. cs e 5v, v cc e 5v, v dd e 5v, reset e 0v, a 0 e 0v, test 0 e 5v, clock applied or inter- nal oscillator operating, bus floating, prog e 5v. 3. test 0 e 0v (select program mode) 4. ea e 12.75v (active program mode) 5. v cc e 6.25v (programming supply) 6. v dd e 12.75v (programming power) 7. address applied to bus and p 2023 8. reset e 5v (latch address) 9. data applied to bus 10. prog e 5v followed by one 100 m s pulse to 0v 11. test 0 e 5v (verify mode) 12. read and verify data on bus 13. test 0 e 0v 14. reset e 0v and repeat from step 6 15. programmer should be at conditions of step 1 when the 87c42 is removed from socket please follow the quick-pulse programming flow chart for proper programming procedure shown in figure 6. 9
upi-c42/upi-l42 290414 14 figure 6. quick-pulse programming algorithm quick-pulse programming algorithm as previously stated, the upi-c42 will be pro- grammed using the quick-pulse programming algo- rithm, developed by intel to substantially reduce the thorughput time in production programming. the quick-pulse programming algorithm uses initial pulses of 100 m s followed by a byte verification to determine when the address byte has been suc- cessfully programmed. up to 25 100 m s pulses per byte are provided before a failure is recognized. a flow chart of the quick-pulse programming algo- rithm is shown in figure 6. the entire sequence of program pulses and byte verifications is performed at v cc e 6.25v and v dd e 12.75v. when programming has been com- pleted, all bytes should be compared to the original data with v cc e v dd e 5v. a verify should be performed on the programmed bits to ensure that they have been correctly pro- grammed. the verify is performed with t0 e 5v, v dd e 5v, ea e 12.75v, ss y e 5v, prog e 5v, a0 e 0v, and cs y e 5v. in addition to the quick-pulse programming algo- rithm, the upi-c42 opt is also compatible with in- tel's int e ligent programming algorithm which is used to program the nmos upi-42ah otp devices. the entire sequence of program pulses and byte verifications is performed at v cc e 6.25v and v dd e 12.75v. when the int e ligent programming cycle has been completed, all bytes should be com- pared to the original data with v cc e 5.0, v dd e 5v. verify a verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. the verify is performed with t0 e 5v, v dd e 5v, ea e 12.75v, ss e 5v, prog e 5v, a0 e 0v, and cs e 5v. security bit the security bit is a single eprom cell outside the eprom array. the user can program this bit with the appropriate access code and the normal program- ming procedure, to inhibit any external access to the eprom contents. thus the user's resident program is protected. there is no direct external access to this bit. however, the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not. the security bit has no effect on the signature mode, so the security byte can always be examined. security bit programming/ verification programming a. read the security byte of the signature mode. make sure it is 00h. 10
upi-c42/upi-l42 b. apply access code to appropriate inputs to put the device into security mode. c. apply high voltage to ea and v dd pins. d. follow the programming procedure as per the quick-pulse programming algorithm with known data on the databus. not only the security bit, but also the security byte of the signature row is pro- grammed. e. verify that the security byte of the signature mode contains the same data as appeared on the data bus. (if db0 db7 e high, the security byte will contain ffh.) f. read two consecutive known bytes from the eprom array and verify that the wrong data are retrieved in at least one verification. if the eprom can still be read, the security bit may have not been fully programmed though the se- curity byte in the signature mode has. verification since the security bit address overlaps the address of the security byte of the signature mode, it can be used to check indirectly whether the security bit has been programmed or not. therefore, the security bit verification is a mere read operation of the security byte of the signature row (0ffh e security bit pro- grammed; 00h e security bit unprogrammed). note that during the security bit programming, the reading of the security byte does not necessarily indicate that the security bit has been successfully pro- grammed. thus, it is recommended that two consec- utive known bytes in the eprom array be read and the wrong data should be read at least once, be- cause it is highly improbable that random data coin- cides with the correct ones twice. signature mode the upi-c42 has an additional 64 bytes of eprom available for intel and user signatures and miscella- neous purposes. the 64 bytes are partitioned as fol- lows: a. test code/checksume this can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory. the test code/checksum is present on roms, and otps. b. intel signature ethis allows the programmer to read from the upi-41ah/42ah/c42 the manu- facturer of the device and the exact product name. it facilitates automatic device identification and will be present in the rom and otp ver- sions. location 10h contains the manufacturer code. for intel, it is 89h. location 11h contains the device code. the code is 43h and 42h for the 8042ah/80c42 and otp 8742ah/87c42, respectively. the code is 44h for any device with the security bit set by intel. c. user signature ethe user signature memory is implemented in the eprom and consists of 2 bytes for the customer to program his own signa- ture code (for identification purposes and quick sorting of previously programmed materials). d. test signature ethis memory is used to store testing information such as: test data, bin num- ber, etc. (for use in quality and manufacturing control). e. security byte ethis byte is used to check whether the security bit has been programmed (see the security bit section). f. upi-c42 intel signature eapplies only to chmos device. location 20h contains the man- ufacturer code and location 21h contains the de- vice code. the intel upi-c42 manufacturer's code is 99h. the device id's are 82h for the otp version and 83h for the rom version. the device id's are the same for the upi-l42. the signature mode can be accessed by setting p10 e 0, p11 p17 e 1, and then following the pro- gramming and/or verification procedures. the loca- tion of the various address partitions are as shown in table 3. sync mode the sync mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time. the sync mode may also be utilized by automatic test equipment (ate) for quick, easy, and efficient synchronizing between the tester and the dut (de- vice under test). sync mode is enabled when ss pin is raised to high voltage level of a 12 volts. to begin synchroniza- tion, t0 is raised to 5 volts at least four clock cycles after ss . t0 must be high for at least four x2 clock cycles to fully reset the prescaler and time state generators. t0 may then be brought down during low state of x2. two clock cycles later, with the ris- ing edge of x2, the device enters into time state 1, phase 1. ss is then brought down to 5 volts 4 clocks later after t0. reset is allowed to go high 5 tcy (75 clocks) later for normal execution of code. 11
upi-c42/upi-l42 table 3. signature mode table address device no. of type bytes test code/checksum 0 0fh rom/otp 25 16h 1eh intel signature 10h 11h rom/otp 2 user signature 12h 13h otp 2 test signature 14h 15h rom/otp 2 security byte 1fh or 3fh rom/otp 2 upi-c42 intel signature 20h 21h rom/otp 2 user defined upi-c42 otp eprom space 22h 3eh rom/otp 30 access code the following table summarizes the access codes required to invoke the sync mode, signature mode, and the security bit, respectively. also, the programming and verification modes are included for comparison. control signals data bus access code modes port 2 port 1 t0 rst ss ea prog v dd v cc 01234567 0123 0 1 234567 programming 0 0 1 hv 1 v ddh v cc address addr a 0 a 1 xxxxxx mode 0 1 1 hv stb v ddh v cc data in addr verification 0 0 1 hv 1 v cc v cc address addr a 0 a 1 xxxxxx mode 111hv1v cc v cc data out addr sync mode stb 0 hv 0 x v cc v cc xxxxxxxxxxx xx xxxxxx high signature prog 0 0 1 hv 1 v ddh v cc addr. (see sig mode table) 0 0 0 0 1 1 1 1 x x 1 mode 0 1 1 hv stb v ddh v cc data in 0 0 0 verify 0 0 1 hv 1 v cc v cc addr. (see sig mode table) 0 0 0 111hv1v cc v cc data out 0 0 0 security prog 0 0 1 hv 1 v ddh v cc address 0 0 0 bit/byte 0 1 1 hv stb v ddh v cc data in 0 0 0 verify 0 0 1 hv 1 v cc v cc address 0 0 0 111hv1v cc v cc data out 0 0 0 note: 1. a 0 e 0or1;a 1 e 0or1.a 0 must e a 1 . 12
upi-c42/upi-l42 sync mode timing diagrams 290414 15 minimum specifications sync operation time, t sync e 3.5 xtal 2 clock cycles. reset time, t rs e 4t cy . note: the rising and falling edges of t0 should occur during low state of xtal 2 clock. applications 290414 12 figure 7. upi-c42 keyboard controller 290414 9 figure 8. 8088-upi-c42 interface 13
upi-c42/upi-l42 applications (continued) 290414 10 figure 9. 8048h-upi-c42 interface 290414 11 figure 10. upi-c42-8243 keyboard scanner 290414 13 figure 11. upi-c42 80-column matrix printer interface 14
upi-c42/upi-l42 absolute maximum ratings * ambient temperature under bias 0 cto a 70 c storage temperature b 65 cto a 150 c voltage on any pin with respect to ground b 0.5v to a 7v power dissipation 1.5 w notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. dc characteristics t a e 0 cto a 70 c, v cc e v dd ea 5v g 10%; a 3.3v g 10% upi-l42 symbol parameter upi-c42 upi-l42 units notes min max min max v il input low voltage b 0.5 0.8 b 0.3 a 0.8 v all pins v ih input high voltage 2.0 v cc 2.0 v cc a 0.3 v (except xtal2, reset) v ih1 input high voltage 3.5 v cc 2.0 v cc a 0.3 v (xtal2, reset) v ol output low voltage (d 0 d 7 ) 0.45 0.45 v i ol e 2.0 ma upi-c42 i ol e 1.3 ma upi-l42 v ol1 output low voltage 0.45 0.45 v i ol e 1.6 ma upi-c42 (p 10 p 17 ,p 20 p 27 , sync) i ol e 1 ma upi-l42 v ol2 output low voltage (prog) 0.45 0.45 v i ol e 1.0 ma upi-c42 i ol e 0.7 ma upi-l42 v oh output high voltage (d 0 d 7 ) 2.4 2.4 v i oh eb 400 m a upi-c42 i oh eb 260 m a upi-l42 v oh1 output high voltage 2.4 2.4 i oh eb 50 m a upi-c42 (all other outputs) i oh eb 25 m a upi-l42 i il input leakage current g 10 g 10 m av ss s v in s v cc (t 0 ,t 1 , rd, wr, cs, a 0 , ea) i ofl output leakage current g 10 g 10 m av ss a 0.45 s v out s v cc (d 0 d 7 , high z state) i li low input load current b 50 b 250 b 35 b 175 m a port pins (p 10 p 17 ,p 20 p 27 ) min v in e 2.4v max v in e 0.45v i li1 low input load current b 40 b 40 m av in s v il (reset, ss) i hi port sink current 5.0 ma v cc e 3.0v (p 10 p 17 ,p 20 p 27 )v ih e 5.0v i dd v dd supply current 4 2.5 ma 15
upi-c42/upi-l42 dc characteristics t a e 0 cto a 70 c, v cc e v dd ea 5v g 10%; a 3.3v g 10% upi-l42 (continued) symbol parameter upi-c42 upi-l42 units notes min max min max i cc a i dd total supply current: active mode @ 12.5 mhz 30 20 ma typical 14 ma upi-c42, 9 ma upi-l42 suspend mode 40 26 m a osc. off (1, 4) i dd standby power down 5 3.5 ma nmos compatible power down mode supply current i ih input leakage current 100 100 m av in e v cc (p 10 p 17 ,p 20 p 27 ) c in input capacitance 10 10 pf t a e 25 c (1) c io i/o capacitance 20 20 pf t a e 25 c (1) note: 1. sampled, not 100% tested. dc characteristicseprogramming (upi-c42 and upi-l42) t a e 25 c g 5 c, v cc e 6.25v g 0.25v, v dd e 12.75v g 0.25v symbol parameter min max units v ddh v dd program voltage high level 12.5 13 v (1) v ddl v dd voltage low level 4.75 5.25 v v ph prog program voltage high level 2.0 5.5 v v pl prog voltage low level b 0.5 0.8 v v eah input high voltage for ea 12.0 13.0 v (2) v eal ea voltage low level b 0.5 5.25 v i dd v dd high voltage supply current 50.0 ma i ea ea high voltage supply current 1.0 ma (4) notes: 1. voltages over 13v applied to pin v dd will permanently damage the device. 2. v eah must be applied to ea before v ddh and removed after v ddl . 3. v cc must be applied simultaneously or before v dd and must be removed simultaneously or after v dd . 4. sampled, not 100% tested. 16
upi-c42/upi-l42 ac characteristics t a e 0 cto a 70 c, v ss e 0v, v cc e v dd ea 5v g 10%; a 3.3v g 10% for the upi-l42 note: all ac characteristics apply to both the upi-c42 and upi-l42 dbb read symbol parameter min max units t ar cs, a 0 setup to rd v 0ns t ra cs, a 0 hold after rd u 0ns t rr rd pulse width 160 ns t ad cs, a 0 to data out delay 130 ns t rd rd v to data out delay 0 130 ns t df rd u to data float delay 85 ns dbb write symbol parameter min max units t aw cs, a 0 setup to wr v 0ns t wa cs, a 0 hold after wr u 0ns t ww wr pulse width 160 ns t dw data setup to wr u 130 ns t wd data hold after wr u 0ns 17
upi-c42/upi-l42 ac characteristics t a e 0 cto a 70 c, v ss e 0v, v cc e v dd ea 5v g 10%; a 3.3v g 10% for the upi-l42 (continued) clock symbol parameter min max units t cy upi-c42/upi-l42 cycle time 1.2 9.20 m s (1) t cyc upi-c42/upi-l42 clock period 80 613 ns t pwh clock high time 30 ns t pwl clock low time 30 ns t r clock rise time 10 ns t f clock fall time 10 ns note: 1. t cy e 15/f(xtal) ac characteristics dma symbol parameter min max units t acc dack to wr or rd 0 ns t cac rd or wr to dack 0 ns t acd dack to data valid 0 130 ns t crq rd or wr to drq cleared 110 ns (1) note: 1. c l e 150 pf. ac characteristics port 2 symbol parameter f(t cy ) (3) min max units t cp port control setup before falling edge of prog 1/15 t cy b 28 55 ns (1) t pc port control hold after falling edge of prog 1/10 t cy 125 ns (2) t pr prog to time p2 input must be valid 8/15 t cy b 16 650 ns (1) t pf input data hold time 0 150 ns (2) t dp output data setup time 2/10 t cy 250 ns (1) t pd output data hold time 1/10 t cy b 80 45 ns (2) t pp prog pulse width 6/10 t cy 750 ns notes: 1. c l e 80 pf. 2. c l e 20 pf. 3. t cy e 1.25 m s. 18
upi-c42/upi-l42 ac characteristicseprogramming (upi-c42 and upi-l42) t a e 25 c g 5 c, v cc e 6.25v g 0.25v, v ddl ea 5v g 0.25v, v ddh e 12.75v g 0.25v (87c42/87l42 only) symbol parameter min max units t aw address setup time to reset u 4t cy t wa address hold time after reset u 4t cy t dw data in setup time to prog v 4t cy t wd data in hold time after prog u 4t cy t pw initial program pulse width 95 105 m s t tw test 0 setup time for program mode 4t cy t wt test 0 hold time after program mode 4t cy t do test 0 to data out delay 4t cy t ww reset pulse width to latch address 4t cy t r ,t f prog rise and fall times 0.5 100 m s t cy cpu operation cycle time 2.5 3.75 m s t re reset setup time before ea u 4t cy t opw overprogram pulse width 2.85 78.75 ms (1) t de ea high to v dd high 1t cy notes: 1. this variation is a function of the iteration counter value, x. 2. if test 0 is high, t do can be triggered by reset u . ac testing input/output waveform input/output 290414 16 ac testing load circuit 290414 17 19
upi-c42/upi-l42 driving from an external source 290414 18 note: see xtal1 configuration table. 290414 19 rise and fall times should not exceed 10 ns. resistors to v cc are needed to ensure v ih e 3.5v if ttl circuitry is used. lc oscillator mode l c nominal f e 1 2 q 0 lc 45 h 20 pf 5.2 mhz 120 h 20 pf 3.2 mhz c e c a 3cpp 2 cpp j 510 pf pin-to-pin capacitance 290414 20 each c should be approximately 20 pf, including stray capacitance. crystal oscillator mode 290414 21 c1 5 pf (stray 5 pf) c2 (crystal a stray) 8 pf c3 20 30 pf including stray crystal series resistance should be less than 30 x at 12.5 mhz. xtal1 configuration table xtal1 connection 1) to ground 2) 10 k x resistor 3) not connected to ground not recommended for chmos recommended configuration for low power configuration designs. causes approximately designs which will use both recommended for chmos only 16 ma of additional current flow nmos and chmos parts. this designs to provide lowest through the xtal1 pin on upi- configuration limits the additional possible power consumption. c42 and approximately 11 ma of current through the xtal1 pin to this configuration will not work additional current through xtal1 approximately 1 ma, while with the nmos device. on the upi-l42. maintaining compatibility with the nmos device. 20
upi-c42/upi-l42 waveforms read operationedata bus buffer register 290414 22 write operationedata bus buffer register 290414 23 clock timing 290414 24 21
upi-c42/upi-l42 waveforms (continued) combination program/verify mode 290414 25 notes: 1. a 0 must be held low (0v) during program/verify modes. 2. for v ih ,v ih1 ,v il ,v il1 ,v ddh , and v ddl , please consult the d.c. characteristics table. 3. when programming the 87c42, a 0.1 m f capacitor is required across v dd and ground to suppress spurious voltage transients which can damage the device. verify mode 290414 26 notes: 1. prog must float if ea is low. 2. prog must float or e 5v when ea is high. 3. p 10 p 17 e 5v or must float. 4. p 24 p 27 e 5v or must float. 5. a 0 must be held low during programming/verify modes. 22
upi-c42/upi-l42 waveforms (continued) dma 290414 27 port 2 290414 28 port timing during external access (ea) 290414 29 on the rising edge of sync and ea is enabled, port data is valid and can be strobed. on the trailing edge of sync the program counter contents are available. 23
upi-c42/upi-l42 table 4. upi instruction set mnemonic description bytes cycles accumulator add a, rr add register to a 1 1 add a, @ rr add data memory 1 1 to a add a, y data add immediate to a 2 2 addc a, rr add register to a 1 1 with carry addc a, @ rr add data memory 1 1 to a with carry addc a, y data add immediate 2 2 to a with carry anl a, rr and register to a 1 1 anl, a @ rr and data memory 1 1 to a anl a, y data and immediate to a 2 2 orl a, rr or register to a 1 1 orl, a, @ rr or data memory 1 1 to a orl a, y data or immediate to a 2 2 xrl a, rr exclusive or regis- 1 1 ter to a xrl a, @ rr exclusive or data 1 1 memory to a xrl a, y data exclusive or imme- 2 2 diate to a inc a increment a 1 1 dec a decrement a 1 1 clr a clear a 1 1 cpl a complement a 1 1 da a decimal adjust a 1 1 swap a swap nibbles of a 1 1 rl a rotate a left 1 1 rlc a rotate a left through 1 1 carry rr a rotate a right 1 1 rrc a rotate a right 1 1 through carry input/output in a, pp input port to a 1 2 outl pp, a output a to port 1 2 anl pp, y data and immediate to 2 2 port orl pp, y data or immediate to 2 2 port in a, dbb input dbb to a, 1 1 clear ibf out dbb, a output a to dbb, 1 1 set obf mov sts, a a 4 a 7 to bits 4 7 of 1 1 status movd a, pp input expander 1 2 port to a movd pp, a output a to 1 2 expander port anld pp, a and a to expander 1 2 port orld pp, a or a to expander 1 2 port mnemonic description bytes cycles data moves mov a, rr move register to a 1 1 mov a, @ rr move data memory 1 1 to a mov a, y data move immediate to a 2 2 mov rr, a move a to register 1 1 mov @ rr, a move a to data 1 1 memory mov rr, y data move immediate to 2 2 register mov @ rr, move immediate to 2 2 y data data memory mov a, psw move psw to a 1 1 mov psw, a move a to psw 1 1 xch a, rr exchange a and 1 1 register xch a, @ rr exchange a and 1 1 data memory xchd a, @ rr exchange digit of a 1 1 and register movp a, @ a move to a from 1 2 current page movp3, a, @ a move to a from 1 2 page 3 timer/counter mov a, t read timer/counter 1 1 mov t, a load timer/counter 1 1 strt t start timer 1 1 strt cnt start counter 1 1 stop tcnt stop timer/counter 1 1 en tcnti enable timer/ 1 1 counter interrupt dis tcnti disable timer/ 1 1 counter interrupt control * en a20 enable a20 logic 1 1 en dma enable dma hand- 1 1 shake lines en i enable ibf interrupt 1 1 dis i diable ibf inter- 1 1 rupt en flags enable master 1 1 interrupts * sel pmb0 select program 1 1 memory bank 0 * sel pmb1 select program 1 1 memory bank 1 sel rb0 select register 1 1 bank 0 sel rb1 select register 1 1 bank 1 * upi-c42/upi-l42 only. 24
upi-c42/upi-l42 table 4. upi instruction set (continued) mnemonic description bytes cycles control (continued) * suspend invoke suspend power- 1 2 down mode nop no operation 1 1 registers inc rr increment register 1 1 inc @ rr increment data 1 1 memory dec rr decrement register 1 1 subroutine call addr jump to subroutine 2 2 ret return 1 2 retr return and restore 1 2 status flags clr c clear carry 1 1 cpl c complement carry 1 1 clr f0 clear flag 0 1 1 cpl f0 complement flag 0 1 1 clr f1 clear f1 flag 1 1 cpl f1 complement f1 flag 1 1 mnemonic description bytes cycles branch jmp addr jump unconditional 2 2 jmpp @ a jump indirect 1 2 djnz rr, addr decrement register 2 2 and jump jc addr jump on carry e 12 2 jnc addr jump on carry e 02 2 jz addr jump on a zero 2 2 jnz addr jump on a not zero 2 2 jt0 addr jump on t0 e 122 jnt0 addr jump on t0 e 022 jt1 addr jump on t1 e 122 jnt1 addr jump on t1 e 022 jf0 addr jump on f0 flag e 12 2 jf1 addr jump on f1 flag e 12 2 jtf addr jump on timer flag 2 2 e 1, clear flag jnibf addr jump on ibf flag 2 2 e 0 jobf addr jump on obf flag 2 2 e 1 jbb addr jump on accumula- 2 2 for bit * upi-c42/upi-l42 only. revision summary the following has been changed since revision -003: 1. delete all references to standby power down mode. the following has been changed since revision -002: 1. added information on keyboard controller prod- uct family. 2. added i hi specification for the upi-l42. the following has been changed since revision -001: 1. added upi-l42 references and specification. 25

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